To quote from his comment on xorloser's blog, linked above:
I just release my lv2 kernel decrypter You need metldr, lv2ldr, RL_FOR_PROGRAM.img and lv2_kernel.self. You have first to dump your metldr from FLASH memory. lv2ldr you will find also in your FLASH memory or in decrypted CORE_OS_PACKAGE.pkg from PUP files.
RL_FOR_PROGRAM.img is a revoke list for programs and can be also found in PUP files. lv2_kernel.self is on your FLASH memory or in decrypted CORE_OS_PACKAGE.pkg.
First i send all files to PS3 and store them in memory. After that i load metldr in isolation mode and pass it the addr e ss of lv2ldr. The code is very low level and many things are done by directly manipulating SPU registers
If you have any questions or problems then feel free to contact me or ask here. I will try to help you. I will try to document my findings on my homepage
I also uploaded a code which can communicate with USB Dongle AUthenticator by using Dispatcher Manager without using any GameOS functions It’s exactly what GameOS does, just low level
Have fun guys
lv2_kernel.self from 1.10 firmware decrypted
Guys, just to make sure that you know LV2 decrypter is also PS2 emu decrypter, just change LPAR auth id in code PS2 emu is like GameOS, it’s LV2 and is decrypted by lv2ldr
Just decrypted vsh.self from 1.10 firmware Just like old good days
I decrypted software_update_plugin.sprx but didn’t have time to reverse it yet
Physical/Virtual memory address of an isolation module that should be loaded by metldr is written into SPU register SPU_In_Mbox. The SPU register SPU_In_Mbox is 32bit, so 64bit memory address is written in 2 steps.
MFC relocation is turned off by clearing R-bit in SPU register MFC_SR1. By doing this, HV enables real address mode for MFC of SPU.
On GameOS, it also works with relocation on. You just have to initialize SLB of SPU and insert valid SLB entries.
Physical/Virtual memory address of metldr is written to SPU registers Sig_Notify1 and Sig_Notify2
Isolation load request is enabled by writing SPU register SPU_PrivCntl
Isolation load request is made by writing value 0x3 into SPU register SPU_RunCntl
SPE_load_request_metldr - 0x002B00A4 (3.15)
lv2ldr is used to decrypt lv2_kernel.self
syscalls 0x10042 and 0x1004A use lv2ldr
syscall 0x10042 is used by HV Process 3 during LV2 LPAR construction
syscall 0x1004A uses different parameters as syscall 0x10042
SPE_load_request_lv2ldr_1 - 0x002AE82C (3.15)
SPE_load_request_lv2ldr_2 - 0x002AE8D8 (3.15)
64 bit memory address of lv2ldr is written into 32 bit SPU register SPU_In_Mbox
metldr is loaded
Decrypting SELFs with appldr and lv1_undocumented_function_99
lv1_undocumented_function_99 loads and prepares appldr for SELF decryption.
When appldr is ready to decrypt data, it sends a message via mailbox.
The address and the size of the encrypted data is passed to appldr via a shared memory.
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A thought: What is the bandwidth on the ribbon cable going to the usb controller chip? Replace that, and make the new chip control usb, wifi and and bluetooth, and leave the internal cell to do the dirty work.
An obvious drawback they would require certain firmwares and liscensed installers to do such, which they would probably look at the device to see if its jb'd too.
I also think this isn't an add-on for the ps3 to enhance it... rather add PS2 backwards compatibility, but I highly doubt that while they still sell PS2's. It has to be for something else or something that will never see production. The processing power of the ps3 is still relevant to today. It's the graphics and memory that is the weak link. No way to fix that without a new board, period. Simply look back in history, this is how the console market is.
Take a look at the 360... there is no way M$ could add on anything to make it faster. Sony will not be doing so either. If for some odd reason Sony could do this and actually did, then M$ would simply release the xbox 720 and blow it away. Not happening
It's most likely disabled to increase yields. Sony/IBM probably had (have?) a ridiculous amount of defective ones and decided to disable 1/8 of the SPEs to make use of all those defective chips they had. Meaning they can't just enable the 8th one because on a lot of PS3s it's defective and can't function properly.
As for an add-on, I'm all for it assuming things are actually programmed to make use of it... AFAIK a lot of ports are butchered because they simply make use of the one core/PPE while all 7 functioning SPEs are left idle. That and the RSX is weaker than the Xenos and the PS3's memory is not shared (256MB XDR system memory and 256MB GDDR3 on the RSX)... also it doesn't have 10MB of eDRAM, lol.