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  1. #271
    Contributor semitope's Avatar
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    Today I validated my theories about running the isolated SPUs on the PS3 as crypto engines. The PS3 is 100% hacked. So where my homebrew at?
    What did Geohot do?

  2. #272
    Forum Moderator PS3 News's Avatar
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    Quote Originally Posted by semitope View Post
    What did Geohot do?
    Unfortunately nobody here is a mindreader, so until he publishes his "theories" it would be a waste of time to speculate on tweets like that.

    Edit: I see he has now updated his blog with more specific details, as follows:
    On the Isolated SPUs

    Today I verified my theories about running the isolated SPUs as crypto engines. So to people like this, sorry you are wrong.

    In OtherOS, all 7 SPUs are idle. You can command an SPU (which I'll leave as an exercise to the reader) to load metldr, from that load the loader of your choice, and from that decrypt what you choose, everything from pkgs to selfs. Including those from future versions.

    The PPU is higher on the control chain then the SPUs. Even if checks were to be added to, for example, verify the hypervisor before decrypting the kernel, with clever memory mappings you can hide your modified hypervisor.

    Ah, but you still didn't get the Cell root key. And I/we never will. But it doesn't matter. For example, we don't have either the iPhone or PSP "root key". But I don't think anyone doubts the hackedness of those systems.

    I wonder if any systems out there are actually secure?
    So basically he's saying according to his research iQD's theory isn't correct is all.

  3. #273
    Registered User Tender Phantom's Avatar
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    George states that you can decrypt pkgs, would I be right in thinking that includes the files extracted from updates? If so then I'm guessing it would make it easier for people to analyse the firmware for possible "bugs"

  4. #274
    Contributor h3lder's Avatar
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    I understand it like this (correct me if I'm wrong):

    The problem now is to be solved by cryptoanalysis. Pkgs are visible now - but that's not a big deal - they are encrypted! So are firmware update downloadable files.

    I understand Geohot is saying that now "we" can try to decrypt this files from the inside (don't imagine how) - and because of that inside approach it will be easy(er).

  5. #275
    Senior Member Pcsx2006's Avatar
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    What i get from his update is the now he can command/force any of spus to decrypt any pkgs or selfs and even modified/make a custom hypervisor would it means he can run unsigned code or maybe i'm all wrong.

  6. #276
    Contributor dante489's Avatar
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    so what now? can we say that the ps3 entire system is down or what?

  7. #277
    Registered User worstenbroodje's Avatar
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    sounds interesting? or is this just something that was already known?

  8. #278
    Senior Member ekrboi's Avatar
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    he has already figured out the "how".. what he is saying is that he can now force the spu to decrypt pkgs or selfs.. I would assume he can use them to decrypt anything.

  9. #279
    Registered User worstenbroodje's Avatar
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    Here is a blog comment from geohot. could be something useful..
    George Hotz said...

    If someone wants to be useful, and can code in a little "language" I created, help me out.

    [Register or Login to view links] is an Instruction Set Descriptor File For EDA, my disassembler. Someone pick up the syntax and finish it, SPU docs are public

    To see what EDA is [Register or Login to view links]
    Code:
    # SPU Instruction Set Descriptor File
    #   by geohot
    # part of "The Embedded Disassembler"
    
    # Registers is a reserved keyword
    # Makes Registers_0 Registers_1 Registers_2... in global scope
    # Haha, that would've been nice if true
    # I don't think % is a reserved keyword
    Registers 128 %0 %1 %2 %3 %4 %5 %6 %7 %8 %9
    Registers 128 %10 %11 %12 %13 %14 %15 %16 %17 %18 %19
    Registers 128 %20 %21 %22 %23 %24 %25 %26 %27 %28 %29
    Registers 128 %30 %31 %32 %33 %34 %35 %36 %37 %38 %39
    Registers 128 %40 %41 %42 %43 %44 %45 %46 %47 %48 %49
    Registers 128 %50 %51 %52 %53 %54 %55 %56 %57 %58 %59
    Registers 128 %60 %61 %62 %63 %64 %65 %66 %67 %68 %69
    Registers 128 %70 %71 %72 %73 %74 %75 %76 %77 %78 %79
    Registers 128 %80 %81 %82 %83 %84 %85 %86 %87 %88 %89
    Registers 128 %90 %91 %92 %93 %94 %95 %96 %97 %98 %99
    Registers 128 %100 %101 %102 %103 %104 %105 %106 %107 %108 %109
    Registers 128 %110 %111 %112 %113 %114 %115 %116 %117 %118 %119
    Registers 128 %120 %121 %122 %123 %124 %125 %126 %127
    Registers 32 PC
    
    # Special Strings
    ProgramCounter `PC`
    LinkRegister `%R0`
    StackPointer `%R1`
    ProgramCounterOffset 0
    
    # Instruction Comprehesions start here
    # An instruction runs through all matching until it hits Stop
    # * is don't care
    # spaces are ignored
    # any lowercase letter is a local variable
    # DefaultChange, Registers are special global words
    # Stop, Change, Parsed are special local words
    # Everything else is a string, with all whitespace stripped
    # Curly braces mean insert variable, undeclared vars are empty
    
    # Parsed
    #   Parsed can be recursive, use percent to insert
    #   |...| is eval string to hex
    
    # Noob notes
    #   |...| is eval string to hex
    #   {...} is get variable
    #   {{...}} is get register indexed by variable
    #   [...] is dereference
    #   `...` is "address of"
    
    # So to clarify, [`{{n}}`] is the derefenced address of the register indexed by the variable "n". Got that?
    # Though I don't understand {|{ri}|} for immeds, why the second get variable
    
    # DefaultChanges apply to the inverse condition of anything targeting the target
    # If that makes sense at all
    
    # I don't think signed(as in like + and -) is handled yet
    
    # This will not be a simulator for now
    
    ####DefaultChanges####
    
    DefaultChange 32 `PC` [`PC`]+4
    
    ####Memory-Load/Store Instructions####
    
    # Load Quadword (d-form)
    00110100 iiiiiiiiii aaaaaaa ttttttt
      ri {i} << 4
      Parsed "O R, I(R)" lqd {{t}} {|{ri}|} {{a}}
      #Change 128 `{{t}}` [[`{{a}}`] + {ri}]
      Stop
    
    # Load Quadword (x-form)
    00111000100 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" lqx {{t}} {{a}} {{b}}
      #Change 128 `{{t}}` [[`{{a}}`] + [`{{b}}`]]
      Stop
    
    # Load Quadword (a-form)
    001100001 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" lqa {{t}} {|{i}|}
      #Change 128 `{{t}}` {i}
      Stop
    
    # Load Quadword Instruction Relative (a-form)
    001100111 iiiiiiiiiiiiiiii ttttttt
      Source [[`PC`] + ({i} << 2)]
      Parsed "O R, I" lqr {{t}} {|Source|}
      #Change 128 `{{t}}` {Source}
      Stop
    
    # Store Quadword (d-form)
    00100100 iiiiiiiiii aaaaaaa ttttttt
      ri {i} << 4
      Parsed "O R, I(R)" stqd {{t}} {|{ri}|} {{a}}
      #Change 128 [`{{a}}`]+{ri} [`{{t}}`]
      Stop
    
    # Store Quadword (x-form)
    00101000100 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" stqx {{t}} {{a}} {{b}}
      #Change 128 [`{{a}}`] + [`{{b}}`] [`{{t}}`]
      Stop
    
    # Store Quadword (a-form)
    001000001 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" stqa {{t}} {|{i}|}
      #Change 128 {i} [`{{t}}`]
      Stop
    
    # Store Quadword Instruction Relative (a-form)
    001000111 iiiiiiiiiiiiiiii ttttttt
      Source [[`PC`] + ({i} << 2)]
      Parsed "O R, I" stqr {{t}} {|Source|}
      #Change 128 {Source} [`{{t}}`]
      Stop
    
    # Generate Controls for Byte Insertion (d-form)
    00111110100 iiiiiii aaaaaaa ttttttt
      Parsed "O R, I(R)" cbd {{t}} {i} {{a}}
      Stop
    
    # Generate Controls for Byte Insertion (x-form)
    00111010100 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" cbx {{t}} {{a}} {{b}}
      Stop
    
    # Generate Controls for Halfword Insertion (d-form)
    00111110101 iiiiiii aaaaaaa ttttttt
      Parsed "O R, I(R)" chd {{t}} {i} {{a}}
      Stop
    
    # Generate Controls for Halfword Insertion (x-form)
    00111010101 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" chx {{t}} {{a}} {{b}}
      Stop
    
    # Generate Controls for Word Insertion (d-form)
    00111110110 iiiiiii aaaaaaa ttttttt
      Parsed "O R, I(R)" cwd {{t}} {i} {{a}}
      Stop
    
    # Generate Controls for Word Insertion (x-form)
    00111010110 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" cwx {{t}} {{a}} {{b}}
      Stop
    
    # Generate Controls for Doubleword Insertion (d-form)
    00111110111 iiiiiii aaaaaaa ttttttt
      Parsed "O R, I(R)" cdd {{t}} {i} {{a}}
      Stop
    
    # Generate Controls for Doubleword Insertion (x-form)
    00111010111 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" cdx {{t}} {{a}} {{b}}
      Stop
    
    ####Constant-Formation Instructions####
    
    # Immediate Load Halfword
    010000011 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" ilh {{t}} {i}
      Stop
    
    # Immediate Load Halfword Upper
    010000010 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" ilhu {{t}} {i}
      Stop
    
    # Immediate Load Word
    010000001 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" il {{t}} {i}
      Stop
    
    # Immediate Load Address
    0100001 iiiiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" ila {{t}} {i}
      Stop
    
    # Immediate Or Halfword Lower
    011000001 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" iohl {{t}} {i}
      Stop
    
    # Form Select Mask for Bytes Immediate
    001100101 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" fsmbi {{t}} {i}
      Stop
    
    ####Integer and Logical Instructions####
    
    # Add Halfword
    00011001000 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" ah {{t}} {{a}} {{b}}
      Stop
    
    # Add Halfword Immediate
    00011101 iiiiiiiiii aaaaaaa tttttt
      Parsed "O R, R, I" ahi {{t}} {{a}} {i}
      Stop
    
    # Add Word
    00011001000 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" a {{t}} {{a}} {{b}}
      Stop
    
    # Add Word Immediate
    00011100 iiiiiiiiii aaaaaaa tttttt
      Parsed "O R, R, I" ai {{t}} {{a}} {i}
      Stop
    
    # Subtract from Halfword
    00001001000 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" sfh {{t}} {{a}} {{b}}
      Stop
    
    # Subtract from Halfword Immediate
    00001101 iiiiiiiiii aaaaaaa tttttt
      Parsed "O R, R, I" sfhi {{t}} {{a}} {i}
      Stop
    
    # Subtract from Word
    00001000000 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" sf {{t}} {{a}} {{b}}
      Stop
    
    # Subtract from Word Immediate
    00001100 iiiiiiiiii aaaaaaa tttttt
      Parsed "O R, R, I" sfi {{t}} {{a}} {i}
      Stop
    
    # Add Extended
    01101000000 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" addx {{t}} {{a}} {{b}}
      Stop
    
    # Carry Generate
    00011000010 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" cg {{t}} {{a}} {{b}}
      Stop
    
    # Carry Generate Extended
    01101000010 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" cgx {{t}} {{a}} {{b}}
      Stop
    
    # Subtract from Extended
    01101000001 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" sfx {{t}} {{a}} {{b}}
      Stop
    
    # Borrow Generate
    00001000010 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" bg {{t}} {{a}} {{b}}
      Stop
    
    # Multiply
    01111000100 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" mpy {{t}} {{a}} {{b}}
      Stop
    
    # Multiply Unsigned
    01111001100 bbbbbbb aaaaaaa tttttt
      Parsed "O R, R, R" mpyu {{t}} {{a}} {{b}}
      Stop
    
    # Multiply Unsigned
    01110100 iiiiiiiiii aaaaaaa tttttt
      Parsed "O R, R, I" mpyi {{t}} {{a}} {i}
      Stop
    Updated Version:
    Code:
    # SPU Instruction Set Descriptor File
    # by geohot
    # part of "The Embedded Disassembler"
     
    # Registers is a reserved keyword
    # Makes Registers_0 Registers_1 Registers_2... in global scope
    # Haha, that would've been nice if true
    # I don't think % is a reserved keyword
    Registers 128 %0 %1 %2 %3 %4 %5 %6 %7 %8 %9
    Registers 128 %10 %11 %12 %13 %14 %15 %16 %17 %18 %19
    Registers 128 %20 %21 %22 %23 %24 %25 %26 %27 %28 %29
    Registers 128 %30 %31 %32 %33 %34 %35 %36 %37 %38 %39
    Registers 128 %40 %41 %42 %43 %44 %45 %46 %47 %48 %49
    Registers 128 %50 %51 %52 %53 %54 %55 %56 %57 %58 %59
    Registers 128 %60 %61 %62 %63 %64 %65 %66 %67 %68 %69
    Registers 128 %70 %71 %72 %73 %74 %75 %76 %77 %78 %79
    Registers 128 %80 %81 %82 %83 %84 %85 %86 %87 %88 %89
    Registers 128 %90 %91 %92 %93 %94 %95 %96 %97 %98 %99
    Registers 128 %100 %101 %102 %103 %104 %105 %106 %107 %108 %109
    Registers 128 %110 %111 %112 %113 %114 %115 %116 %117 %118 %119
    Registers 128 %120 %121 %122 %123 %124 %125 %126 %127
    Registers 32 PC
     
    # Special Strings
    ProgramCounter `PC`
    LinkRegister `%R0`
    StackPointer `%R1`
    ProgramCounterOffset 0
     
    # Instruction Comprehesions start here
    # An instruction runs through all matching until it hits Stop
    # * is don't care
    # spaces are ignored
    # any lowercase letter is a local variable
    # DefaultChange, Registers are special global words
    # Stop, Change, Parsed are special local words
    # Everything else is a string, with all whitespace stripped
    # Curly braces mean insert variable, undeclared vars are empty
     
    # Parsed
    # Parsed can be recursive, use percent to insert
    # |...| is eval string to hex
     
    # Noob notes
    # |...| is eval string to hex
    # {...} is get variable
    # {{...}} is get register indexed by variable
    # [...] is dereference
    # `...` is "address of"
     
    # So to clarify, [`{{n}}`] is the derefenced address of the register indexed by the variable "n". Got that?
    # Though I don't understand {|{ri}|} for immeds, why the second get variable
     
    # DefaultChanges apply to the inverse condition of anything targeting the target
    # If that makes sense at all
     
    # I don't think signed(as in like + and -) is handled yet
     
    # This will not be a simulator for now
    
    # Update by Disane some of the Integer and Logical Instructions were wrong so i had to correct them
    # missing t -s and the Add Word bit mask was wrong
    # also added new instructions
    # i could not confirm if the (d-form) and (a-form) instructions in Memory-Load/Store Instructions are valid
    
    ####DefaultChanges####
     
    DefaultChange 32 `PC` [`PC`]+4
     
    ####Memory-Load/Store Instructions####
     
    # Load Quadword (d-form)
    00110100 iiiiiiiiii aaaaaaa ttttttt
      ri {i} << 4
      Parsed "O R, I(R)" lqd {{t}} {|{ri}|} {{a}}
      #Change 128 `{{t}}` [[`{{a}}`] + {ri}]
      Stop
     
    # Load Quadword (x-form)
    00111000100 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" lqx {{t}} {{a}} {{b}}
      #Change 128 `{{t}}` [[`{{a}}`] + [`{{b}}`]]
      Stop
     
    # Load Quadword (a-form)
    001100001 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" lqa {{t}} {|{i}|}
      #Change 128 `{{t}}` {i}
      Stop
     
    # Load Quadword Instruction Relative (a-form)
    001100111 iiiiiiiiiiiiiiii ttttttt
      Source [[`PC`] + ({i} << 2)]
      Parsed "O R, I" lqr {{t}} {|Source|}
      #Change 128 `{{t}}` {Source}
      Stop
     
    # Store Quadword (d-form)
    00100100 iiiiiiiiii aaaaaaa ttttttt
      ri {i} << 4
      Parsed "O R, I(R)" stqd {{t}} {|{ri}|} {{a}}
      #Change 128 [`{{a}}`]+{ri} [`{{t}}`]
      Stop
     
    # Store Quadword (x-form)
    00101000100 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" stqx {{t}} {{a}} {{b}}
      #Change 128 [`{{a}}`] + [`{{b}}`] [`{{t}}`]
      Stop
     
    # Store Quadword (a-form)
    001000001 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" stqa {{t}} {|{i}|}
      #Change 128 {i} [`{{t}}`]
      Stop
     
    # Store Quadword Instruction Relative (a-form)
    001000111 iiiiiiiiiiiiiiii ttttttt
      Source [[`PC`] + ({i} << 2)]
      Parsed "O R, I" stqr {{t}} {|Source|}
      #Change 128 {Source} [`{{t}}`]
      Stop
     
    # Generate Controls for Byte Insertion (d-form)
    00111110100 iiiiiii aaaaaaa ttttttt
      Parsed "O R, I(R)" cbd {{t}} {i} {{a}}
      Stop
     
    # Generate Controls for Byte Insertion (x-form)
    00111010100 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" cbx {{t}} {{a}} {{b}}
      Stop
     
    # Generate Controls for Halfword Insertion (d-form)
    00111110101 iiiiiii aaaaaaa ttttttt
      Parsed "O R, I(R)" chd {{t}} {i} {{a}}
      Stop
     
    # Generate Controls for Halfword Insertion (x-form)
    00111010101 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" chx {{t}} {{a}} {{b}}
      Stop
     
    # Generate Controls for Word Insertion (d-form)
    00111110110 iiiiiii aaaaaaa ttttttt
      Parsed "O R, I(R)" cwd {{t}} {i} {{a}}
      Stop
     
    # Generate Controls for Word Insertion (x-form)
    00111010110 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" cwx {{t}} {{a}} {{b}}
      Stop
     
    # Generate Controls for Doubleword Insertion (d-form)
    00111110111 iiiiiii aaaaaaa ttttttt
      Parsed "O R, I(R)" cdd {{t}} {i} {{a}}
      Stop
     
    # Generate Controls for Doubleword Insertion (x-form)
    00111010111 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" cdx {{t}} {{a}} {{b}}
      Stop
     
    ####Constant-Formation Instructions####
     
    # Immediate Load Halfword
    010000011 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" ilh {{t}} {i}
      Stop
     
    # Immediate Load Halfword Upper
    010000010 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" ilhu {{t}} {i}
      Stop
     
    # Immediate Load Word
    010000001 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" il {{t}} {i}
      Stop
     
    # Immediate Load Address
    0100001 iiiiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" ila {{t}} {i}
      Stop
     
    # Immediate Or Halfword Lower
    011000001 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" iohl {{t}} {i}
      Stop
     
    # Form Select Mask for Bytes Immediate
    001100101 iiiiiiiiiiiiiiii ttttttt
      Parsed "O R, I" fsmbi {{t}} {i}
      Stop
     
    ####Integer and Logical Instructions####
     
    # Add Halfword
    00011001000 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" ah {{t}} {{a}} {{b}}
      Stop
     
    # Add Halfword Immediate
    00011101 iiiiiiiiii aaaaaaa ttttttt
      Parsed "O R, R, I" ahi {{t}} {{a}} {i}
      Stop
     
    # Add Word
    00011000000 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" a {{t}} {{a}} {{b}}
      Stop
     
    # Add Word Immediate
    00011100 iiiiiiiiii aaaaaaa ttttttt
      Parsed "O R, R, I" ai {{t}} {{a}} {i}
      Stop
     
    # Subtract from Halfword
    00001001000 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" sfh {{t}} {{a}} {{b}}
      Stop
     
    # Subtract from Halfword Immediate
    00001101 iiiiiiiiii aaaaaaa ttttttt
      Parsed "O R, R, I" sfhi {{t}} {{a}} {i}
      Stop
     
    # Subtract from Word
    00001000000 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" sf {{t}} {{a}} {{b}}
      Stop
     
    # Subtract from Word Immediate
    00001100 iiiiiiiiii aaaaaaa ttttttt
      Parsed "O R, R, I" sfi {{t}} {{a}} {i}
      Stop
     
    # Add Extended
    01101000000 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" addx {{t}} {{a}} {{b}}
      Stop
     
    # Carry Generate
    00011000010 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" cg {{t}} {{a}} {{b}}
      Stop
     
    # Carry Generate Extended
    01101000010 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" cgx {{t}} {{a}} {{b}}
      Stop
     
    # Subtract from Extended
    01101000001 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" sfx {{t}} {{a}} {{b}}
      Stop
     
    # Borrow Generate
    00001000010 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" bg {{t}} {{a}} {{b}}
      Stop
     
    # Multiply
    01111000100 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" mpy {{t}} {{a}} {{b}}
      Stop
     
    # Multiply Unsigned
    01111001100 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" mpyu {{t}} {{a}} {{b}}
      Stop
     
    # Multiply Immediate
    01110100 iiiiiiiiii aaaaaaa ttttttt
      Parsed "O R, R, I" mpyi {{t}} {{a}} {i}
      Stop
    
    # Multiply Unsigned Immediate
    01110101 iiiiiiiiii aaaaaaa ttttttt
      Parsed "O R, R, I" mpyui {{t}} {{a}} {i}
      Stop
    
    # Multiply and Add
    1100 ttttttt bbbbbbb aaaaaaa ccccccc
      Parsed "O R, R, R, R" mpya {{t}} {{a}} {{b}} {{c}}
      Stop
    
    # Multiply High
    01111000101 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" mpyh {{t}} {{a}} {{b}}
      Stop
    
    # Multiply and Shift Right
    01111000111 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" mpys {{t}} {{a}} {{b}}
      Stop
    
    # Multiply High High
    01111000110 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" mpyhh {{t}} {{a}} {{b}}
      Stop
    
    # Multiply High High and Add
    01101000110 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" mpyhha {{t}} {{a}} {{b}}
      Stop
    
    # Multiply High High Unsigned
    01111001110 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" mpyhhu {{t}} {{a}} {{b}}
      Stop
    
    # Multiply High High Unsigned and Add
    01101001110 bbbbbbb aaaaaaa ttttttt
      Parsed "O R, R, R" mpyhhau {{t}} {{a}} {{b}}
      Stop
    
    # Count Leading Zeros

  10. #280
    Registered User lilstevie's Avatar
    Join Date
    Dec 2009
    Posts
    17

    Arrow

    That source is for a processor module for his disassembler that he created, having worked with EDA in the past it would be nice for an SPU library to exist, its much more intuitive than IDA.
    Last edited by lilstevie; 02-14-2010 at 08:39 AM Reason: added missing words from post

 

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