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Thread: it might help

  1. #1
    Registered User fonky2mars's Avatar
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    Lightbulb it might help

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    there's something i have found on the cell processor a pdf document of 876 pages i have thought it could help someone i have also some .bz2 files on the cell processor i'll be able to give them to everyone

    there are the title of the documents i were not able to upload it:
    Code:
    List of Tables
    Table 1-1. Definition of Threads and Tasks ............................................................................................ 42
    Table 2-1. PowerPC Data Types ............................................................................................................. 51
    Table 2-2. PowerPC Instruction Summary .............................................................................................. 53
    Table 2-3. Vector/SIMD Multimedia Extension Instruction Summary ...................................................... 58
    Table 3-1. LS-Access Arbitration Priority and Transfer Size ................................................................... 66
    Table 3-2. SPE Floating-Point Support ................................................................................................... 69
    Table 3-3. SPU Instruction Summary ...................................................................................................... 75
    Table 4-1. PPE Memory Management Unit Features ............................................................................. 81
    Table 4-2. PTE Fields .............................................................................................................................. 87
    Table 4-3. Decoding for Large Page Sizes ............................................................................................. 90
    Table 4-4. Summary of Implemented WIMG Settings ............................................................................. 91
    Table 4-5. TLB Compare-Tag Width ....................................................................................................... 94
    Table 4-6. TLB Software Management ................................................................................................... 96
    Table 4-7. Supported Invalidation Selector (IS) Values in the tlbiel Instruction ....................................... 98
    Table 4-8. Summary of Real Addressing Modes ................................................................................... 100
    Table 4-9. Summary of Real-Mode Attributes ....................................................................................... 100
    Table 4-10. Real-Mode Storage Control Values ..................................................................................... 100
    Table 4-11. SPE Synergistic Memory Management Unit Features ......................................................... 102
    Table 4-12. SLB and TLB Compare Tags ............................................................................................... 109
    Table 4-13. SMM_HID Page-Size Decoding ........................................................................................... 112
    Table 4-14. MFC_TLB_Invalidate_Entry Index Selection ....................................................................... 114
    Table 4-15. Translation, MMIO, and Address Match-Generated Exceptions .......................................... 117
    Table 5-1. Memory-Base Registers Loaded by Configuration Ring ...................................................... 123
    Table 5-2. CBE Memory Map ................................................................................................................ 124
    Table 5-3. PPE Privileged Memory-Mapped Register Groups .............................................................. 126
    Table 5-4. Predefined Real-Address Locations ..................................................................................... 127
    Table 5-5. SPE Problem-State Memory-Mapped Register Groups ....................................................... 129
    Table 5-6. SPE Privilege-State-2 Memory-Mapped Register Groups ................................................... 129
    Table 5-7. SPE Privilege-State-1 Memory-Mapped Register Groups ................................................... 129
    Table 6-1. Atomic-Unit Commands ....................................................................................................... 153
    Table 6-2. Address Range Registers (One per PPE Thread) ............................................................... 156
    Table 7-1. IOIF Mask and Size of Address Range ................................................................................ 175
    Table 7-2. Memory Coherence Requirements for I/O Accesses ........................................................... 190
    Table 7-3. Ordering of Inbound I/O Accesses from Same or Different I/O Addresses .......................... 192
    Table 7-4. Ordering of Inbound I/O Accesses from Different I/O Addresses ........................................ 192
    Table 8-1. Tokens Needed for EIB or IOIF Operations in Single-CBE Systems ................................... 207
    Table 8-2. Memory Tokens Available Based on TKM_CR[MT] ............................................................. 217
    Table 8-3. OR and AND Values for All RAG Priorities .......................................................................... 224
    this is only the first page of the table there are 867 pages i'll find a way to release it on the site

  2. #2
    Toucan Sam CJPC's Avatar
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    It is appreciated, but If I am not mistaken that is part of the released documents by IBM. If so, it has already been released- so thanks for the effort!

 

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