AES has a fixed [Register or Login to view links] of 128 [Register or Login to view links] and a [Register or Login to view links] of 128, 192, or 256 bits, whereas Rijndael can be specified with block and key sizes in any multiple of 32 bits, with a minimum of 128 bits. The blocksize has a maximum of 256 bits, but the keysize has no theoretical maximum.
AES operates on a 4×4 [Register or Login to view links] matrix of bytes, termed the state (versions of Rijndael with a larger block size have additional columns in the state). Most AES calculations are done in a special finite field.
The AES cipher is specified as a number of repetitions of transformation rounds that convert the input plaintext into the final output of ciphertext. Each round consists of several processing steps, including one that depends on the encryption key. A set of reverse rounds are applied to transform ciphertext back into the original plaintext using the same encryption key.
High-level description of the algorithm
KeyExpansion—round keys are derived from the cipher key using [Register or Login to view links]
AddRoundKey—each byte of the state is combined with the round key using bitwise xor
SubBytes—a non-linear substitution step where each byte is replaced with another according to a [Register or Login to view links].
ShiftRows—a transposition step where each row of the state is shifted cyclically a certain number of steps.
MixColumns—a mixing operation which operates on the columns of the state, combining the four bytes in each column.
Final Round (no MixColumns)
The SubBytes step
In the SubBytes step, each byte in the matrix is updated using an 8-bit [Register or Login to view links], the [Register or Login to view links]. This operation provides the non-linearity in the [Register or Login to view links]. The S-box used is derived from the [Register or Login to view links] over [Register or Login to view links](28), known to have good non-linearity properties. To avoid attacks based on simple algebraic properties, the S-box is constructed by combining the inverse function with an invertible [Register or Login to view links]. The S-box is also chosen to avoid any fixed points (and so is a [Register or Login to view links]), and also any opposite fixed points.
The ShiftRows step
The ShiftRows step operates on the rows of the state; it cyclically shifts the bytes in each row by a certain [Register or Login to view links]. For AES, the first row is left unchanged. Each byte of the second row is shifted one to the left. Similarly, the third and fourth rows are shifted by offsets of two and three respectively. For the block of size 128 bits and 192 bits the shifting pattern is the same. In this way, each column of the output state of the ShiftRows step is composed of bytes from each column of the input state. (Rijndael variants with a larger block size have slightly different offsets). In the case of the 256-bit block, the first row is unchanged and the shifting for second, third and fourth row is 1 byte, 3 bytes and 4 bytes respectively—this change only applies for the Rijndael cipher when used with a 256-bit block, as AES does not use 256-bit blocks.
The MixColums step
In the MixColumns step, the four bytes of each column of the state are combined using an invertible [Register or Login to view links]. The MixColumns function takes four bytes as input and outputs four bytes, where each input byte affects all four output bytes. Together with ShiftRows, MixColumns provides [Register or Login to view links] in the cipher.
During this operation, each column is multiplied by the known matrix that for the 128 bit key is
The multiplication operation is defined as: multiplication by 1 means leaving unchanged, multiplication by 2 means shifting byte to the left and multiplication by 3 means shifting to the left and then performing [Register or Login to view links] with the initial unshifted value. After shifting, a conditional [Register or Login to view links] with 0x11B should be performed if the shifted value is larger than 0xFF.
In more general sense, each column is treated as a polynomial over GF(28) and is then multiplied modulo x4+1 with a fixed polynomial c(x) = 0x03 · x3 + x2 + x + 0x02. The coefficients are displayed in their [Register or Login to view links] equivalent of the binary representation of bit polynomials from GF(2)[x]. The MixColumns step can also be viewed as a multiplication by a particular [Register or Login to view links] in a [Register or Login to view links]. (This is further explained here: [Register or Login to view links] )
The AddRoundKey step
In the AddRoundKey step, the subkey is combined with the state. For each round, a subkey is derived from the main [Register or Login to view links] using [Register or Login to view links]; each subkey is the same size as the state. The subkey is added by combining each byte of the state with the corresponding byte of the subkey using bitwise [Register or Login to view links].
Optimization of the cipher
On systems with 32-bit or larger words, it is possible to speed up execution of this cipher by combining SubBytes and ShiftRows with MixColumns, and transforming them into a sequence of table lookups. This requires four 256-entry 32-bit tables, which utilizes a total of four kilobytes (4096 bytes) of memory—one kilobyte for each table. A round can now be done with 16 table lookups and 12 32-bit exclusive-or operations, followed by four 32-bit exclusive-or operations in the AddRoundKey step.
If the resulting four kilobyte table size is too large for a given target platform, the table lookup operation can be performed with a single 256-entry 32-bit (i.e. 1 kilobyte) table by the use of circular rotates.
Test vectors are a set of known ciphers for a given input and key. [Register or Login to view links] distributes the reference of AES test vectors as [Register or Login to view links]
Using a byte-oriented approach, it is possible to combine the SubBytes, ShiftRows, and MixColumns steps into a single round operation.
You can clearly see the 6 pins left side of the chip. Two of them have trace. Those two traces are U_RS232_RXD and U_RS232_TXD, enoguh to get RS232 to work. Now it says 3.3V standby. I think I need to keep the TV in standby mode so that the board will have enoguh current for the rs232 port and the chips to operate.
I will take a look at this tomorrow. The weekend is here!
Ok guys I need help here. I can not connect RS232 directly to the debug port. That's why I have ordered a USB/TTL converter.
CP2102 based USB/RS232 Transfer circuit
Built-in USB to RS232 Transfer chip.
Designed to be used for USB to TTL electronic projects.
TTL interface output, easy to connect to your MCU.
Dual 3.3V and 5V Power output, work with 3.3v and 5v target device.
Compact design. V1.0
Now the question is, there are 3 GND pins on the port:
If I was doing this, I would have attached to both of them, seems like enough grounding for 3.3. But I'm a slacker when it comes to hardware-things, so you may not bother listening to me before someone else, more qualified answers you
Awesome progress, BTW, that thing what you're doing, it's cool.